The present invention relates to flash memories. More particularly, the present invention relates to simultaneous operation flash memory chip architectures having flexible bank partitions.
Electronic systems often include a processor and memory. The memory in these electronic systems stores program instructions for the processor (i.e. code) and data. In many systems the code and/or data must be retained when power to the system is withdrawn. A type of memory that performs this retaining function is known as non-volatile memory. Some electronic devices, which use non-volatile memory, include personal computers, personal digital assistants, cellular telephones and digital cameras. For examples, a cellular telephone uses non-volatile memory to store telephone numbers and a personal computer uses non-volatile memory to store the computer""s BIOS (basic input/output system).
There are a variety of non-volatile memory types. One commonly used type is flash memory. Flash memory devices have a memory array of flash transistors configured in rows and columns. A wordline decoder (also referred to as an X-decoder) provides operational voltages to rows of transistors within pre-defined sectors of the memory array. The wordline decoder is typically connected to the gates of the flash transistors within a given sector. A bit line decoder (also referred to as a Y-decoder) provides operational voltages to columns of transistors and is typically connected to the drains of the flash transistors within each column. Usually, the sources of all the flash transistors are coupled to a common sourceline, which is controlled by a sourceline controller.
A limitation of the conventional flash memory described above relates to the differences in time it takes to perform a read operation compared to the time it takes to perform either a program operation or an erase operation. Program and erase cycles for typical flash memory devices are much longer than read access times. This disparity limits the speed of operation of systems in which such a memory is used.
To overcome this problem, a modified flash memory device, known as a simultaneous operation flash memory device, has been developed. In a typical simultaneous operation flash memory device, the flash memory array is partitioned into an upper memory bank and a lower memory bank. The upper and lower memory banks are normally used for different purposes. For example, the upper memory bank may be used for code storage, whereas the lower memory bank may be used for data storage. Although the simultaneous operation flash memory device is an improvement, it has a limitation of its own in that the partitioning of the upper and lower banks is fixed in the design. Such memory devices are, therefore, limited to applications that are compatible with the fixed memory partition.
To overcome the rigidity of the fixed memory partition scheme, U.S. Pat. No. 5,995,415 to Kuo et al. proposes a flash memory device having a flexible bank partition architecture. In this patent, Kuo et al. teach how bit lines of a memory array can be flexibly partitioned to form upper and lower memory banks. Because the bit lines of the memory array are split to make the partition, however, an additional column decoder (i.e. y-decoder) is required to implement the design. This not only renders the design more complex, it also limits the area available for forming the memory array portion of the flash memory device.
Generally, a simultaneous operation flash memory chip architecture having a flexible memory bank partition for forming first and second memory banks from a plurality of flash memory arrays and a method of forming the same are disclosed. The partition is defined by selecting one of a plurality of preformed metal masks, which allows the formation and extension of pre-decoded address lines to inputs of decoders associated with the first and second memory banks, respectively.
According to an aspect of the invention a method of forming a simultaneous operation dual-bank flash memory device comprises steps of providing a plurality of flash memory arrays, providing row and column decoders for each flash memory array and partitioning the plurality of flash memory arrays into a first memory bank and a second memory bank by coupling first bank row and column address lines between first bank row and column pre-decoders and the row and column decoders associated with the first memory bank, and by coupling second bank row and column address lines between second bank row and column pre-decoders and the row and column decoders associated with the second memory bank.
According to another aspect of the invention, a method of forming a dual-bank flash memory device comprises steps of: providing a plurality of flash memory arrays, each memory array having associated row and column address decoders and partitioning the flash memory arrays into a first memory bank and a second memory bank. Partitioning the flash memory arrays into first and second memory banks is accomplished by forming first bank pre-decoded column address lines and coupling them between a first bank column address pre-decoder and the column address decoders associated with the first bank, forming second bank pre-decoded column address lines and coupling them between a second bank column address pre-decoder and the column address decoders associated with the second bank, forming first bank pre-decoded row address lines and coupling them between a first bank row address pre-decoder and the row address decoders associated with the first bank, and forming second bank pre-decoded row address lines and coupling them between a second bank row address pre-decoder and the row address decoders associated with the second bank. According to this aspect of the invention, the sizes of the first and second memory banks are variable, depending upon selection from and application of one a plurality of preformed metal masks used to perform the step of partitioning.
According to another aspect of the invention, a simultaneous operation flash memory device having a flexible dual-bank architecture comprises a plurality of memory arrays capable of being partitioned into a first memory bank and a second memory bank. The partitioning of arrays within the first and second memory banks is determined by how pre-decoded row and address lines are formed during a process used to fabricate the device.
According to yet another embodiment of the present invention, a simultaneous operation flash memory chip having a flexible memory bank partition comprises a plurality of memory arrays having associated row and column decoders, said plurality of memory arrays partitioned into first and second memory banks, a first bank column address pre-decoder coupled to the column address decoders associated with the first memory bank, a first bank row address pre-decoder coupled to the row address decoders associated with the first memory bank, a second bank column address pre-decoder coupled to the column address decoders associated with the second memory bank, and a second bank row address pre-decoder coupled to the row address decoders associated with the second memory bank.
A further understanding of the nature and the advantages of the inventions disclosed herein is described now in reference to the remaining portions of the specification and the attached drawings.